The present disclosure relates generally to integrated circuit design, and more specifically, to using net-based target congestion ratios in global routing.
The design of the layout of an integrated circuit typically includes both global routing and detailed routing. Global routing is used to find a rough path for each net by defining routing regions and generating a tentative route that specifies a set of routing regions traversed for each net being routed. During the global routing process, each net is assigned to a set of routing regions however the actual layout of wires is not specified. The actual layout of wires used by the nets is typically specified during detailed routing. During detailed routing, for each routing region, each net that passing through that region is assigned particular routing tracks and the layout of the wires is fixed.
Routing has a big impact on the yield of integrated circuits. Some common problems affected by routing that can lead to yield loss include random open defects and random short defects. Random open defects are defects that can occur when wire width is too small. Random short defects are defects that can occur when wire spacing is too small. Wire spreading in global routing is a technique that has been used to improve yield in routing.